China is accelerating work on next‑generation “2D chips” built from atom‑thin semiconductor materials, as Shanghai switches on the country’s first engineering‑scale 2D‑chip production line and researchers report wafer‑scale fabrication at speeds up to about 1,000‑fold faster than conventional methods. The moves signal a concerted effort to carve out a distinct, equipment‑light advanced‑chip pathway as Western‑controlled lithography tools remain scarce.
Two‑dimensional chips use materials only a few atoms thick—such as molybdenum disulfide or indium selenide—instead of traditional three‑dimensional silicon, enabling tighter transistor scaling, lower leakage power, and improved heat management. In recent years, Chinese teams have published early‑stage 2D processors and memory prototypes, including the Nature‑published Lingyu CPU built with about 5,900 MoS₂ transistors and a standard‑cell library, and the Chang Ying (CY‑01) 2D‑silicon hybrid flash‑memory chip from Fudan University’s Zhou Peng and Liu Chunsen group, which achieved near‑94% cell yield and high operating speed.
At the fabrication front, a team led by Zhu Mengjian at the National University of Defence Technology has reported a modified chemical vapor deposition technique using a liquid‑gold‑tungsten‑based substrate to grow 2D semiconductor films on wafers at speeds roughly 1,000 times higher than earlier approaches. This advance, described in work summarized by technical outlets and reported by South China Morning Post, lets researchers tune electrical doping across the film, easing the transition from lab‑scale 2D devices to integrated circuits compatible with industrial processes. Around the same time, Peking University’s Kaihui Liu and collaborators demonstrated high‑quality wafer‑scale two‑dimensional indium selenide, broadening the palette of manufacturable 2D channel materials.
On the manufacturing‑floor side, Shanghai Atomic Technology, a startup founded in February 2025 by Fudan‑affiliated Bao Wenzhong, has begun operating a roughly 1,000‑square‑meter engineering‑demonstration line in Pudong’s Shanghai Integrated Circuit Technology and Industry Innovation Center. The line supports production of 2D‑based microprocessors sized to sub‑1‑nanometer‑equivalent nodes and has already produced test chips built around the “WUJI” (Infinity) 2D processor, which integrates about 5,900 atom‑thin transistors in a 32‑bit architecture. The chip is designed for low‑power operation and can handle arithmetic on numbers up to roughly 4.2 billion, with gigabyte‑class data throughput, targeting AI and edge‑computing workloads.
Shanghai Atomic aims to fully operationalize the line by June 2026, reach a 90‑nanometer‑equivalent silicon node within the year, progress to 28‑nanometer equivalence by 2027, and target 5‑ or even 3‑nanometer equivalence by 2028–2030. Government‑backed alliances between universities, local authorities, and venture capital are being formed to compress the lab‑to‑factory cycle, with 2D chips seen as a potential “beyond‑Moore” route that reduces dependence on EUV‑lithography‑constrained silicon nodes while supplying radiation‑tolerant, low‑power chips for AI, space, and defense.
