Panmnesia plans to begin supply of its PCIe 6.4–CXL 3.2 fusion switch chip in the second half of the year, targeting next-generation AI data centers and high-performance computing (HPC) environments. The company states that the chip is the first to fully implement the CXL 3.2 standard, including support for port-based routing (PBR).
The fusion switch integrates both PCIe and Compute Express Link (CXL) protocols on a single die. This enables connectivity across a broad range of devices, including PCIe-based GPUs, switches, CXL-enabled CPUs, memory expanders, and AI accelerators. The approach is designed to support increasingly complex and heterogeneous computing architectures.
A key feature of the chip is its support for composable infrastructure at rack scale. This architecture allows compute, memory, and accelerator resources to be pooled and dynamically allocated based on workload demands. The result is improved resource utilization and reduced operational inefficiencies, particularly for large-scale AI workloads such as large language models (LLMs), retrieval-augmented generation (RAG), deep learning recommendation models (DLRM), and scientific simulations.
Panmnesia highlights port-based routing as a major differentiator. Unlike conventional hierarchy-based routing, which limits system design to tree structures centered around CPUs, port-based routing allows devices to be interconnected in flexible topologies. This enables shorter data paths and more efficient communication. The chip also supports both port-based and hierarchy-based routing modes on a single platform.
The switch further supports cascading, allowing multiple chips to be interconnected to create large-scale fabrics across multiple server racks. This enables thousands of devices to operate within a unified system without relying on higher-latency networking technologies such as Ethernet.
In terms of performance, the chip supports all CXL sub-protocols, including CXL.cache, CXL.mem, and CXL.io, enabling cache coherency and reducing unnecessary data transfers. It also supports PCIe Gen 6 speeds of up to 64 gigatransfers per second (GT/s), addressing the increasing bandwidth requirements of modern AI systems.
Panmnesia has incorporated a proprietary ultra-low-latency controller into the design. The company reports latency in the double-digit nanosecond range, with the controller optimized for CXL-based architectures and adaptable for customer-specific configurations.
The fusion switch silicon is currently available for sampling, with early access partners able to evaluate pilot systems. Mass production is scheduled for later this year.
