Rambus Inc. (NASDAQ: RMBS) introduced a DDR5 9600 Server RDIMM chipset on Tuesday, expanding its portfolio of memory interface solutions as artificial intelligence (AI) and high-performance computing (HPC) workloads drive demand for faster server memory.
The chipset is designed for next-generation CPU-based server platforms and supports registered dual in-line memory modules (RDIMMs) operating at speeds of up to 9,600 mega transfers per second (MT/s). At the centre of the platform is Rambus’ sixth-generation Registering Clock Driver (RCD06), which the company said delivers a 20% increase in bandwidth over the previous generation.
The launch comes as hyperscale cloud providers and enterprise data centre operators invest in AI infrastructure to support increasingly complex model training and inference workloads, placing greater demands on server memory bandwidth, capacity and power efficiency.
Rambus said the chipset is intended to address these requirements by improving memory throughput for applications such as agentic AI, large language model (LLM) inference and HPC workloads.
Growing adoption of AI inference has increased memory requirements in data centres as techniques such as key-value (KV) caching require systems to repeatedly store and retrieve contextual information to improve response times while reducing computational overhead. At the same time, newer server processors are incorporating higher core counts and additional memory channels, increasing demand for faster memory subsystems.
“The rapidly accelerating adoption of agentic AI and AI inference workloads is driving unprecedented demand for higher memory bandwidth and capacity in the data center,” Rami Sethi, senior vice president and general manager of Memory Interface Chips at Rambus, said in a statement.
According to the company, the chipset combines the RCD06 with its PMIC5030 power management integrated circuit, designed to deliver stable low-voltage power for advanced DDR5 RDIMM configurations.
The solution also integrates a Serial Presence Detect (SPD) Hub with an onboard temperature sensor, along with dedicated temperature sensor integrated circuits to provide module configuration, thermal monitoring and system telemetry.
By integrating clocking, power management and control functions into a single chipset, Rambus said the platform is intended to simplify memory module design while maintaining signal integrity and system reliability at higher data transfer rates.
“As data center architectures evolve to support increasingly complex workloads, memory bandwidth, latency and reliability are becoming critical system-level design considerations,” Soo Kyoum Kim, associate vice president at IDC, said in a statement.
