Micron Technology has announced the signing of an exclusive Letter of Intent to acquire Powerchip Semiconductor Manufacturing Corporation’s P5 fabrication site in Tongluo, Miaoli County, Taiwan, marking a significant step in its efforts to expand global memory manufacturing capacity. The transaction, valued at US$1.8 billion in cash, is expected to strengthen Micron’s ability to address rising demand for DRAM and other memory solutions.
The proposed acquisition includes an existing 300mm fabrication facility with a cleanroom area of approximately 300,000 square feet. Micron said the facility will complement its current operations in Taiwan and provide additional flexibility as memory demand continues to grow across data centers, artificial intelligence, automotive, and consumer applications.
In addition to the site purchase, the Letter of Intent outlines plans to establish a long-term strategic relationship between Micron and PSMC. Under this arrangement, the companies intend to collaborate on Micron’s post-wafer assembly processing, while Micron will also support PSMC’s legacy DRAM product portfolio. The partnership is positioned as a way to leverage the strengths of both companies while maintaining continuity for existing operations.
Manish Bhatia, executive vice president of global operations at Micron, said the acquisition would enhance the company’s production capabilities and customer responsiveness. He noted that the Tongluo fab’s proximity to Micron’s existing Taichung site is expected to enable operational synergies across Micron’s Taiwan footprint.
The transaction is anticipated to close by the second quarter of calendar year 2026, subject to the finalization of definitive agreements and the receipt of required regulatory approvals. Following the closing, Micron will assume ownership and operational control of the P5 site. The company plans to equip the facility and ramp DRAM production in phases, while PSMC will relocate its Tongluo operations over an agreed period.
Micron expects the Tongluo facility to begin contributing meaningful DRAM wafer output in the second half of calendar year 2027.
