proteanTecs has introduced a suite of health, power and performance management solutions designed to give semiconductor and system companies deeper visibility into multi-die systems as advanced packaging becomes increasingly important to AI computing.
The company said its new capabilities are built on its on-chip monitoring technology and are aimed at improving yield, reducing development and manufacturing risk, and protecting the economics of high-value systems-in-package (SiP).
The shift towards chiplet-based architectures is bringing processors, accelerators, memory and connectivity into increasingly complex multi-die packages. As these components interact within a single package, analysing individual dies separately can make it harder to identify problems created during integration or operation.
proteanTecs said its expanded portfolio combines chiplet quality assurance, pre- and post-packaging correlation, synchronised inter-chiplet analysis and multi-stream data analytics. The approach is designed to provide visibility at the individual chiplet level while also showing how the components behave collectively inside the package.
The company said the technology can identify integration-related effects including thermal gradients, power and clock noise, structural stress and workload-dependent behaviour. The monitoring extends into system operation, providing awareness of thermal conditions, power consumption and timing margins that can be used to optimise performance and reliability in the field.
The move reflects a broader challenge facing semiconductor manufacturers as advanced packaging increases the value of each assembled system. Identifying a marginal die after it has been integrated with other high-value components can raise costs and reduce overall yield.
proteanTecs said its technology can help identify potential risks earlier in the manufacturing process, including during wafer sort, while correlating data before and after package assembly. This can help manufacturers assess known-good-die (KGD) and known-good-stack (KGS) quality and understand changes introduced during packaging.
The company expects the additional visibility to support higher compound yields across multi-die architectures and provide greater insight into package and power-delivery quality. It can also help engineering teams optimise power and performance in systems where thermal and electrical constraints become more difficult to manage as integration increases.
Evelyn Landman, co-founder and CTO of proteanTecs, said advanced packaging creates electrical, thermal and mechanical interactions that conventional pass-fail testing may not capture. Per-chiplet monitoring, she said, can provide insight into how individual dies perform and interact from production through field operation.
The company said it is already deploying the advanced packaging capabilities through multi-year, multi-generation engagements with customers. The work builds on proteanTecs’ existing analytics and monitoring technologies for silicon and systems, including real-time reliability, power and performance optimisation.
