THine Electronics Inc. (Tokyo: 6769) has announced two new optical semiconductor products designed to support high-speed, low-latency connectivity in large-scale AI datacenters as demand for GPU-to-memory bandwidth continues to rise.
The company introduced the THLD6481, a 64 Gbps VCSEL (Vertical-Cavity Surface-Emitting Laser) driver, and the THTA6482, a 64 Gbps transimpedance amplifier (TIA). Both products incorporate THine’s proprietary ZERO EYE SKEW technology and are being developed for PCI Express 6 and PCI Express 7 optical interconnect applications.
A central feature of the new architecture is the removal of digital signal processors (DSPs) from the optical link. THine said its proprietary circuit technology is designed to maintain signal integrity at high data rates without the processing overhead associated with DSP-based architectures. The company expects the approach to reduce latency and power consumption while also enabling higher-density and lower-cost optical interconnects.
The products are aimed at the scale-up infrastructure increasingly required by AI servers, where large numbers of GPUs and other accelerators must exchange data with memory at high speeds. As AI workloads become more computationally intensive, optical links are gaining importance as a means of addressing bandwidth and energy constraints within datacenter systems.
The THLD6481 and THTA6482 are designed to support VCSEL and photodiode arrays, allowing them to be used in high-density optical configurations. THine said this architecture can contribute to improved cost performance as AI datacenter operators scale interconnect capacity.
The company will demonstrate the new chipsets at the European Conference on Optical Communications (ECOC) 2026 in Málaga, Spain, from September 21 to 23.
THine is also developing a PCIe 7 optical chipset based on its ZERO EYE SKEW technology. The next-generation solution is planned to support 128 Gbps per lane and is targeted at near-package optics (NPO) and co-packaged optics (CPO) applications, with samples planned for 2027.
According to THine, the planned PCIe 7 architecture could reduce latency by 90% and power consumption by 73% compared with DSP-based optical interconnects. The figures represent the company’s target performance for the planned technology rather than specifications of the currently announced products.
“As AI use cases continue to expand exponentially, optical interconnect technology will play a pivotal role in enabling Scale-Up AI servers equipped with over 500 xPUs,” said Yasuhiro Takada, chief strategy officer at THine Electronics.
The company said it has also begun planning driver and TIA products for optical interconnects used with UCIe retimers, expanding its focus beyond PCIe-based applications.
The development of the new optical semiconductor products is partly supported by a grant administered by Japan’s National Institute of Information and Communications Technology (NICT), under program JPJ012368G70601.
