Murata Manufacturing Co. (TYO: 6981) has begun mass production of its LLD series of three-terminal low-equivalent series inductance (ESL) multilayer ceramic capacitors (MLCCs), with the company describing them as the world’s smallest of their type.
Measuring 0.6 × 0.3 mm, the 0201-inch components reduce mounting area by approximately 64% compared with Murata’s previous smallest 0402-inch three-terminal MLCCs. The smaller footprint is intended to free PCB space in compact electronics, including smartphones and wearable devices.
Smaller Components for High-Speed ICs
As mobile devices incorporate more powerful integrated circuits, maintaining stable power delivery has become increasingly important. High-speed IC operation can cause rapid changes in current demand, potentially resulting in voltage fluctuations.
Three-terminal capacitors can help address this issue by providing shorter current paths than conventional two-terminal components, resulting in lower ESL and improved high-frequency power supply stability near ICs.
However, reducing the size of three-terminal MLCCs presents manufacturing challenges because their electrode structures are more complex than those used in conventional two-terminal capacitors.
Murata said it addressed the challenge by optimizing its electrode design and advancing manufacturing processes. The resulting 0201-inch components are designed to support high-density mounting while maintaining power supply stability near ICs operating at high frequencies.
Two Models Available
The LLD series currently includes two models, both offering 1 µF capacitance.
The LLD033R60G105ME01 has a rated voltage of 4 Vdc and an operating temperature range of -55°C to +85°C. The LLD033D80E105ME01 is rated at 2.5 Vdc and operates from -55°C to +105°C.
The compact components are intended to provide designers with greater flexibility when placing components around ICs, particularly where PCB space is constrained.
Murata said the new MLCCs can support further miniaturization of mobile and wearable electronics while addressing power integrity requirements associated with higher-performance processors.
