Intel Corporation (NASDAQ: INTC) said its Intel 18A-P process technology has entered risk production, marking a key milestone in the company’s foundry roadmap as it works to strengthen its position in advanced semiconductor manufacturing.
The update was announced at the 2026 VLSI Symposium, where Intel Foundry shared progress on its next-generation process technologies and highlighted research projects aimed at extending chip performance and scaling in the years ahead.
Intel 18A-P is the first performance-enhanced version of the Intel 18A process family. According to the company, the node entered risk production on schedule, in line with commitments made to customers and partners last year.
“Our updates and presentations at VLSI signal to Intel Foundry customers and partners that we are fully committed to leading-edge process innovation over the long term,” said Naga Chandrasekaran, Executive Vice President and General Manager of Intel Foundry.
Intel said the new process delivers measurable gains over the base Intel 18A node. According to the company, Intel 18A-P provides 9% higher performance at the same power level or 18% lower power consumption at the same performance level.
Engineers also introduced a new transistor enhancement called Power Boost. The feature uses a dual-contact, low-resistance transistor design that increases drive current and enables higher operating frequencies.
Other improvements include better thermal performance, lower via resistance, and additional transistor options aimed at balancing performance and power efficiency. Intel said thermal resistance has improved by between 20% and 40%, while via resistance has been reduced by 10% to 30% through design and material optimizations.
The company also added a new logic threshold voltage option, giving chip designers more flexibility when optimizing products for speed and energy efficiency.
A key advantage of Intel 18A-P is its compatibility with Intel 18A design rules. Intel said customers can reuse existing intellectual property and design flows without major redesign efforts, helping simplify migration to the newer process.
Beyond Intel 18A-P, the company provided new insights into gate-all-around (GAA) transistors and backside power delivery (BSPD), technologies introduced with Intel 18A and considered important building blocks for future chip designs.
At the symposium, Intel Foundry Vice President and Fellow Eric Karl presented data on the benefits of backside power delivery. According to Intel, the technology can reduce routed chip area by 11% and cut dynamic voltage droop by as much as ten times compared with traditional frontside power delivery methods.
The company said these improvements can enable up to a 6% increase in operating frequency or more than 15% lower dynamic power consumption.
Intel researchers also shared silicon results from CPU cores built using GAA transistors and BSPD. The company reported approximately 30% higher frequency at low operating voltages of around 0.5 volts, while also reducing power delivery losses and improving efficiency.
Looking further ahead, Intel used the event to showcase research projects focused on future semiconductor scaling.
Among them was work on Complementary Field-Effect Transistors (CFET), which vertically stack NMOS and PMOS transistors. Intel demonstrated monolithic CFET inverters at a 45-nanometer gate pitch, highlighting a potential path beyond current GAA architectures.
The company also demonstrated the integration of gallium nitride (GaN) power devices with silicon logic on 300mm wafers. Intel said the approach could combine digital control functions and power management on a single platform, reducing system complexity.
Another research effort focused on ruthenium-based interconnect technology. Intel reported capacitance reductions of up to 35% compared with copper interconnects, which could help improve performance as chip dimensions continue to shrink.
