Cadence Design Systems has expanded its longstanding collaboration with Taiwan Semiconductor Manufacturing Company, strengthening efforts to accelerate the design and development of next-generation artificial intelligence (AI) and high-performance computing (HPC) silicon.
The enhanced engagement centers on delivering a signoff-ready, end-to-end design infrastructure that combines silicon-proven intellectual property (IP), certified electronic design automation (EDA) flows, and support for advanced process technologies, including TSMC’s N3, N2, A16, and A14 nodes. The approach is intended to help semiconductor companies reduce design iterations, improve correlation across workflows, and accelerate time to silicon.
As AI workloads expand, chip architectures are evolving toward chiplet-based and 3D integrated circuit (3D-IC) designs, increasing design complexity. The collaboration is aligned with design technology co-optimization (DTCO) principles, enabling tighter integration between design tools and manufacturing processes to address performance, power, and area (PPA) trade-offs.
Cadence is contributing an expanded portfolio of advanced-node IP, including high-speed interfaces such as DDR5, PCIe 6.0, LPDDR6/5X, and HBM4E, which are essential for supporting bandwidth-intensive AI and HPC applications. These are complemented by certified EDA flows spanning synthesis, implementation, verification, and signoff, optimized for TSMC’s leading-edge nodes.
A key component of the collaboration is the integration of artificial intelligence into chip design workflows. Cadence is advancing its “AI for Design” strategy by embedding agentic AI into its toolchain, enabling goal-driven automation across the design cycle. This includes the development of “agent-ready” infrastructures that combine domain-specific expertise with physics-based analysis to improve design convergence and engineering productivity.
The partnership also extends to advanced packaging and heterogeneous integration. Cadence’s 3D-IC platforms are aligned with TSMC’s 3DFabric technologies, supporting stacked-die architectures and complex multi-chip systems. These capabilities are increasingly critical as semiconductor companies seek to scale performance beyond traditional node-based improvements.
Industry stakeholders, including NVIDIA and Arm Ltd., have emphasized the importance of ecosystem collaboration in addressing the growing demands of AI-driven computing. The integration of design tools, process technologies, and IP is seen as central to enabling efficient and scalable chip development.
Momentum is building around TSMC’s 3nm and 2nm process technologies, with multiple companies already advancing designs on these nodes. This trend highlights the increasing need for cohesive, validated design environments capable of supporting next-generation silicon innovation.
