Taiwan Semiconductor Manufacturing Co. (NYSE: TSM) is sharply expanding advanced-packaging capacity as the rapid growth of AI accelerators pushes chipmakers to combine larger compute dies with increasing amounts of high-bandwidth memory (HBM).
TSMC expects capacity for its Chip on Wafer on Substrate (CoWoS) and System on Integrated Chips (SoIC) technologies to grow at an annual rate of more than 80% through 2027, Vice President for Operations and Advanced Technology Engineering B.Z. Tien said at the company’s 2026 Taiwan Technology Symposium in Hsinchu.
The pace of expansion underscores how advanced packaging has become a critical part of the AI semiconductor supply chain. As AI accelerators grow in computing performance, integrating processors and HBM in a single package has become increasingly important for delivering the bandwidth required by training and inference workloads.
TSMC said its 5.5-reticle CoWoS platform, which it describes as the world’s largest CoWoS solution, has achieved a yield exceeding 98%. Vice President for Business Development Yuan Li-pen said the technology entered mass production in 2026. The yield figure applies specifically to the 5.5-reticle platform and is not an industry-wide benchmark.
CoWoS is TSMC’s 2.5D packaging technology, allowing multiple dies and HBM stacks to be integrated on a common package. SoIC takes a different approach, using 3D integration to stack semiconductor dies vertically.
The two technologies are becoming increasingly important as AI systems move towards larger accelerator packages. Conventional scaling at the transistor and wafer level alone is becoming insufficient to deliver the bandwidth and memory density required by increasingly complex AI workloads, making the ability to integrate compute and memory efficiently a key differentiator.
TSMC is already preparing for another jump in package size. The company plans to begin production in 2028 of a 14-reticle CoWoS platform capable of integrating 20 HBM chips. A larger version designed to support 24 HBM chips is planned for 2029.
The roadmap reflects the growing memory requirements of AI accelerators, where HBM has become a central component of high-performance computing platforms. Larger packages can allow accelerator designers to connect more memory to compute resources while maintaining high-bandwidth communication between them.
TSMC is expanding wafer manufacturing capacity alongside packaging. The company plans to launch five new fabs in 2026 to address demand for AI chips and 2-nanometre products. It expects 2nm capacity to grow at a compound annual rate of 70% from 2026 to 2028, while CoWoS and SoIC capacity is projected to expand by more than 80% annually through 2027.
The expansion comes as TSMC faces competition from Intel Corp. (NASDAQ: INTC) and Samsung Electronics Co. (KRX: 005930), both of which are developing advanced packaging and foundry technologies. TSMC’s reported CoWoS yield therefore provides a measure of progress on its own platform rather than a direct comparison across competing technologies.
TSMC’s packaging roadmap also comes as demand for advanced process nodes accelerates. The company said it has received about 25 completed 2nm chip designs, with more than 70 additional customer projects in development. Its A16 process remains scheduled for production in the second half of 2026, while A13 and A12 are planned for mass production in 2029.
For TSMC, the investment in advanced packaging is increasingly inseparable from its leading-edge foundry strategy. AI chip demand is creating pressure across the manufacturing chain, from advanced process capacity to HBM integration and package assembly.
