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Cadence and Intel Foundry Expand AI-Driven Chip Design Partnership

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Cadence Design Systems has announced an expanded multi-year collaboration with Intel Foundry aimed at accelerating Design Technology Co-Optimization (DTCO) for Intel’s next-generation process technologies, starting with the upcoming Intel 14A node.

The agreement brings together Cadence’s agentic AI-driven electronic design automation (EDA) tools and Design IP portfolio with Intel Foundry’s process technology and advanced design expertise. The companies said the collaboration is intended to optimize design tools, workflows, and methodologies to improve performance, power efficiency, and silicon area, commonly referred to as PPA.

As part of the initiative, Cadence and Intel will work closely to refine Intel 14A process technology and deliver production-ready Process Design Kits (PDKs) for semiconductor customers. The collaboration will also leverage Cadence’s AI-powered design flows and core software platforms to help reduce design complexity, lower risk, and accelerate time-to-market for advanced chip development.

The announcement reflects a deeper strategic alignment between the two companies as semiconductor manufacturers and design firms increasingly adopt AI-driven methodologies to address growing design complexity in high-performance computing (HPC), mobile, and next-generation applications.

“Advancing our relationship with Intel into a much deeper partnership is a major milestone for both companies,” said Anirudh Devgan, President and Chief Executive Officer of Cadence. He noted that the collaboration is expected to help customers achieve higher levels of performance, power efficiency, and innovation while accelerating the development of future products.

Naga Chandrasekaran said the expanded partnership aligns with Intel Foundry’s focus on executing its technology roadmap and strengthening its ecosystem. According to Chandrasekaran, combining Intel’s process and packaging technologies with Cadence’s AI-driven design solutions will enable deeper co-optimization and support customer requirements for increasingly advanced semiconductor designs.

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