Rambus (NASDAQ: RMBS) has introduced a power management integrated circuit (PMIC) designed for next-generation LPDDR6 Small Outline Compression Attached Memory Modules (SOCAMM2), targeting the power-efficiency requirements of accelerated artificial intelligence infrastructure.
The new chip is being developed in collaboration with customers and ecosystem partners to support future AI servers that require greater memory bandwidth and capacity while managing power consumption. It extends Rambus’ portfolio of power management and memory interface products for LPDDR-based server memory.
As AI training and inference workloads expand, data center operators are increasingly focused on improving computing output relative to energy consumption. For AI systems, this includes maximizing tokens processed per watt, a measure of energy efficiency that is becoming important as inference services and agentic AI applications scale.
LPDDR6 SOCAMM2 is under development and represents the next stage in applying low-power double data rate memory technology to server platforms. The modular architecture is designed to combine LPDDR’s power-efficiency characteristics with a compact, serviceable memory form factor suited to demanding AI workloads.
Rami Sethi, senior vice president and general manager of Memory Interface Chips at Rambus, said the new PMIC builds on the company’s server-memory power management technology and is intended to support memory architectures optimized for performance and energy efficiency.
Micron Technology also highlighted the role of low-power memory in future AI infrastructure. Praveen Vaidyanathan, vice president and general manager of Cloud Memory Products at Micron, said LPDRAM is becoming increasingly important as AI systems place greater demands on memory capacity, bandwidth and power efficiency. He added that Micron continues to work with industry partners on standards such as SOCAMM2.
Power Management for LPDDR6 Modules
The PMIC is designed to regulate the power supplied to LPDDR6 DRAM and other active components on a SOCAMM2 module. It converts the system supply voltage into the levels required by the memory and supporting chips.
Alongside power conversion, the device is designed to support power sequencing, telemetry and fault protection. These functions help manage changing electrical demands, monitor operating conditions and protect module components against power-related faults.
Rambus said the PMIC and its LPDDR6 SOCAMM2 serial presence detect (SPD) Hub are being developed to provide precise, module-level power management for future AI systems. The SPD Hub supports module configuration and related management functions, complementing the PMIC’s power delivery capabilities.
Together, the components are intended to support the performance, reliability and energy efficiency requirements of next-generation accelerated computing platforms.
Extending Rambus’ Server Memory Portfolio
Rambus supplies memory interface chipsets for DDR- and LPDDR-based modules. Its portfolio includes registering clock drivers, PMICs, voltage regulators, SPD Hubs and temperature sensors.
The company already offers an LPDDR5X SOCAMM2 chipset designed to provide power delivery, configuration and telemetry functions for current-generation SOCAMM2 modules. The new PMIC and SPD Hub extend that product roadmap to the developing LPDDR6 standard.
The expansion reflects efforts across the semiconductor industry to develop memory architectures that can meet AI systems’ growing requirements without proportionally increasing power consumption. Memory performance and energy efficiency are important considerations in accelerated computing, where processors must access large volumes of data to sustain high utilization.
Rambus did not disclose pricing, sampling schedules or commercial availability timelines for the new PMIC. The product’s adoption will depend on the development of LPDDR6 SOCAMM2, ecosystem integration and the requirements of future server platforms.
