Teradyne has launched three new automated test equipment instruments for its UltraFLEXplus platform as semiconductor manufacturers face growing testing demands from artificial intelligence and data center computing devices.
The new UltraPin5000-EM, UltraPort-PCIe6 and UltraVS64-HP are designed to support testing across advanced semiconductor development and production, from wafer probe through final system-level validation. Teradyne said the instruments address higher pattern volumes, faster interfaces and rising power requirements associated with next-generation AI and compute devices.
Teradyne (NASDAQ: TER) provides automated test equipment and robotics. The company said the new instruments expand the capabilities of its UltraFLEXplus platform while allowing manufacturers to scale testing as device architectures become more complex.
“As the AI and data center market drives unprecedented growth in semiconductor complexity, Teradyne remains committed to delivering innovative solutions that enable our customers to stay ahead in this rapidly evolving market,” said Greg Smith, CEO of Teradyne.
The UltraPin5000-EM is the company’s next-generation digital instrument for pattern-intensive AI and compute devices. Teradyne said it provides up to 80 times more vector memory than other market offerings, addressing the large test patterns required by complex processors and other compute devices.
The instrument also enables pattern loads up to 10 times faster. Its Persistence Mode is designed to allow near-instant reloads, helping engineering teams accelerate debugging and device characterization while improving equipment utilisation in production environments.
The UltraPin5000-EM supports signal integrity at data rates of up to 5 Gbps. Its timing architecture allows independent clock frequencies for each pin, supporting devices with heterogeneous requirements. A scan network acceleration feature compiles per-core results in real time, enabling adaptive test decisions and potentially reducing structural test time.
The instrument is compatible with Teradyne’s UltraPin2200, allowing manufacturers to extend existing test investments as device requirements evolve.
The UltraPort-PCIe6 addresses high-speed I/O testing for PCIe Gen6 interfaces. Teradyne described it as the industry’s first high-speed I/O protocol automated test equipment solution for PCIe Gen6, supporting 64 Gbps PAM-4 across 32 lanes per instrument.
The instrument combines signal integrity capabilities with per-pin parametric measurement units and integrated loopback functionality. These features are intended to expand test coverage and diagnostics while simplifying test-system setup.
A dedicated server-class computing backend can scale to 2TB of high-performance memory for handling large test datasets. The system supports both mission-mode testing and high-speed I/O scan, allowing some testing to move earlier in the semiconductor manufacturing process.
Teradyne said earlier insertion can improve Known Good Die confidence and help reduce losses involving high-value high-bandwidth memory and advanced packaging assemblies.
The third instrument, the UltraVS64-HP, focuses on power delivery for high-performance compute devices. It can provide up to 1,280 amps per instrument and 5,120 amps when supplies are ganged together. A complete test cell can exceed 15,000 amps, according to the company.
The power supply also features a 16V range intended to support emerging integrated voltage regulator architectures. This enables testing across low-voltage, high-current devices as well as systems requiring higher-voltage inputs.
As advanced packaging moves toward larger and more powerful compute devices, the additional current and voltage capacity is designed to accommodate changing power requirements without requiring a separate instrument for each architecture.
The UltraVS64-HP includes integrated multi-point sensing and dynamic load response to maintain stable conditions as current demand changes across large dies and multi-die packages. Teradyne has also added power profiling capabilities to provide engineers with detailed information on device behaviour during testing.
An Intelligent power interface adds system-level power management functions to the test cell and provides hardware-level fault response. The company said the feature is designed to help prevent thermal runaway and reduce the risk of damage to probe cards and sockets.
